The present invention relates in general to the field of memories. More particularly, the present invention relates to a CMOS memory cell having improved read and write speed as a result of having separate read and write bit lines.
The basic CMOS cross coupled latch, which is well known in the art, forms a basic static storage element. In such a device both the reading and writing of the cell have in the past been accomplished by a single bit line coupled to the cell. This single bit line is ordinarily coupled to a number of separate cells and therefore represents a fairly high capacitive load. The read time would therefore be relatively long in that the memory cell itself would be relied upon to transfer current to the high capacitive load bit line. The CMOS memory cell does not ordinarily provide a high current which could charge the capacitive load of the bit line rapidly.
In addition the coupling device used to couple the bit line to the memory cell during the write cycle has ordinarily been a relatively high impedance device such as an N-channel MOS transistor. This relatively high impedance coupling device tends to limit the write cycle time to a relatively high value. Both the read and write time have therefore been relatively high for those coupling devices previously used between the single bit line and a CMOS cross coupled latch memory cell.